1. Field of the Invention
The invention relates to a phase detection circuit for the purpose of generating a local clock in accordance with the phase difference between two clock signals.
2. Related Art
In the past, to a phase detection circuit, for example, a signal comprising a random binary-coded stream generated by a clock of frequency f0, inputted and the phase detection circuit was used to generate a local clock with both a phase and a frequency synchronized to this clock signal.
For example, the first example of a phase detection circuit according to prior art, shown in FIG. 9, is formed by D-type flip-flops F/F1, F/F2, AND circuits AND1 and AND2, an adder circuit ADD, and a delay circuit DL1. In a phase detection circuit configured in this manner, a first clock signal C1 and a data signal D1 are input, and output signals PDOUT and Q2 are output.
With a phase detection circuit having the configuration of the first example of prior art, the timing of the clock C1 input to the flip-flops F/F1 and F/F2 is the same. Thus, the timing of the signal Q1 input to the flip-flop F/F2 is delayed by a prescribed delay time tpd1.
In the above-noted phase detection circuit of the past, however, there was a need for a further increase in speed. With respect to this need, with the above-noted configuration of the past, the high the signal speed becomes, the more significant becomes the delay time tpd1 of the flip-flop F/F1, thereby reducing the operation margin of the flip-flop F/F2. For this reason, depending upon the operating conditions and variations in the manufacturing conditions of the circuit, if the delay time tpd1 changes, there is a further reduction in the operating margin, thereby leading to the problem of faulty operation.
For example, in the case of a 10-Gb/s NRZ signal, with a clock period T of 100 ps, the delay time tpd1 is approximately 20 to 40 ps, and when the variations in various conditions are considered, the delay time tpd1 becomes approximately 60 ps.
Accordingly, it is an object of the present invention to provide a phase detection circuit that enables the achievement of a sufficient operating margin.
In order to achieve the above noted objects, the present invention adopts the following basic technical constitution.
Specifically, the first aspect of the present invention is a phase detection circuit which detects a phase difference between a data signal D1 and a clock signal C1, the detection circuit comprising: a first D-type flip-flop circuit F/F1, to which the data signal D1 and the clock signal C1 are input; a first delay circuit DL2 which delays the clock signal C1 by a prescribed amount of time, so as to generate a delayed clock signal C1xe2x80x2; a second D-type flip-flop circuit F/F2, to which an output signal Q1 of the first D-type flip-flop circuit F/F1 and the delayed clock signal C1xe2x80x2 are input; a second delay circuit DL1 which delays the output signal Q2 of the second D-type flip-flop circuit F/F2 so as to generate a first delayed signal Q2xe2x80x2, a third delay circuit DL3 which delay the an output signal Q1 of the first D-type flip-flop circuit F/F1 so as to generate a second delayed signal Q1xe2x80x2, a fourth delay circuit DL4 which delays the data signal D1 so as to generate a delayed data signal D1xe2x80x2, a first AND circuit AND2 which calculates a logical product of the first delayed signal Q2xe2x80x2 and the second delayed signal Q1xe2x80x2 so as to output a DOWN signal, a second AND circuit AND1 which calculates a logical product of the second delayed signal Q1xe2x80x2 and the delayed data signal D1xe2x80x2 so as to output an UP signal, and an adder circuit ADD which adds the UP signal and the DOWN signal so as to output a detection signal PDOUT detecting the phase difference between the data signal D1 and the clock signal C1.
In the second aspect of the present invention, the first D-type flip-flop circuit F/F1 operates at rising edge of the clock signal C1 and the second D-type flip-flop circuit F/F2 operates at a falling edge of the delayed clock signal C1xe2x80x2.
In the third aspect of the present invention, to the first AND circuit, the second delayed signal and an inverted signal of the first delayed signal are input, and to the second AND circuit, the delayed data signal and an inverted signal of the second delayed signal are input
The fourth aspect of the present invention is a phase detection circuit which detects a phase difference between a data signal D1 and a clock signal C1, the detection circuit comprising: a first D-type flip-flop circuit F/F1, to which the data signal D1 and the clock signal C1 are input; a first delay circuit DL12 which delays the clock signal C1 by a prescribed amount of time, so as to generate a delayed clock signal C1xe2x80x2; a second D-type flip-flop circuit F/F2, to which an output signal Q1 of the first D-type flip-flop circuit F/F1 and the delayed clock signal C1xe2x80x2are input; a second delay circuit DL13 which delays the an output signal Q1 of the first D-type flip-flop circuit F/F1 so as to generate a first delayed signal Q1xe2x80x2, a third delay circuit DL11 which delays the data signal D1 so as to generate a second delayed signal D1xe2x80x2, a first exclusive-OR circuit XOR2 which calculates a logical product of an output signal Q2 of the second D-type flip-flop circuit F/F2 and the first delayed signal Q1xe2x80x2 so as to output a DOWN signal, a second exclusive-OR circuit XOR1 which calculates a logical product of the first delayed signal Q1xe2x80x2 and the second delayed signal D1xe2x80x2 so as to output an UP signal, and an adder circuit ADD which adds the UP signal and the DOWN signal so as to output a detection signal PDOUT detecting the phase difference between the data signal and the clock signal.